US Patent 11487872 Detection of hardware security attacks

In example implementations, an apparatus is provided. The apparatus includes an input sensor, a memory, a comparator, and a processor. The processor is communicatively coupled to the input sensor, the memory, and the comparator to control operation of the input sensor, the memory, and the comparator. The input sensor is to measure a bus signal of a computing device. The memory is to store the bus signal that is measured and a reference bus signal. The comparator is to compare the bus signal that is measured to the reference bus signal to detect a hardware security attack.