Patent attributes
A barrier synchronization system, a parallel information processing apparatus, and the like are described in the embodiments. In an example, provided is a solution to reduce latency time and improve processing speed in barrier synchronization. The parallel information processing apparatus includes: a completion information storage configured to store completion information, wherein the completion information includes information relating to completion of processing of an own apparatus and information relating to completion of processing of a lower information processing apparatus located in the tree structure; and a control circuit configured to, in response to a determination result indicating that a current status amounts to a given condition, instruct a specified information processing apparatus to forcibly suspend processing, the specified information processing apparatus being an apparatus that has not yet completed processing before all of the plurality of information processing apparatuses have completed the processing.
