Patent attributes
A processing system is disclosed. The processing system includes an amplifier including a multitude of input resistors receiving a multitude of reduced noise signals from a multitude of charge integrators and a summing resistor at an output of the amplifier. The amplifier is configured to generate a feedback signal at the output of the amplifier by amplifying each of a multitude of reduced noise signals using a gain value and a cardinality of the multitude of reduced noise signals. The multitude of charge integrators is configured to obtain a multitude of resulting signals from a multitude of capacitive sensor electrodes coupled to a noise source and generate the multitude of reduced noise signals by mitigating noise in the multitude of the resulting signals, at the multitude of charge integrators, using the feedback signal. Resistances of the multitude of input resistors, a resistance of the summing resistor, and the gain values are selected to mitigate the noise.
