Patent attributes
Techniques are described for controlling operation of a pixel conversion ADC in a manner that enforces strict timing and synchronization of ramp and clock signaling. Synchronizing techniques can be applied to generate a corrected ramp start signal based on synchronizing a received ramp start signal to an input clocking signal, and to generate a controller clock signal based on synchronizing an input clocking signal to the corrected ramp start signal. The corrected ramp start signal and the controller clock signal can be used to control generation of a ramp enable signal for controlling timing of pixel ramp voltage generation digital pixel conversion counting, and to control generation of an output clocking signal used by the digital pixel conversion counting.
