Patent attributes
Image compression circuitry comprises first-stage compression circuitry, first-stage selector circuitry, second-stage compression circuitry, and second-stage selector circuitry. The first-stage compression circuitry is configured to sequentially receive a plurality of input blocks each comprising pixel data of a plurality of pixels, generate a plurality of first-stage compressed blocks by compressing the plurality of input blocks, and generate a plurality of first-stage decompressed blocks. The first-stage selector circuitry is configured to select first-stage-selected decompressed blocks from among the plurality of first-stage decompressed blocks and select first-stage-selected compressed blocks corresponding to the first-stage-selected decompressed blocks from among the plurality of first-stage compressed blocks. The second-stage compression circuitry is configured to generate a plurality of second-stage compressed blocks by compressing the plurality of input blocks and generate a plurality of second-stage decompressed blocks. The second-stage selector circuitry is configured to select second-stage-selected compressed and output the second-stage-selected compressed blocks.
