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US Patent 11403069 Accelerated mathematical engine

Patent 11403069 was granted and assigned to Tesla (company) on August, 2022 by the United States Patent and Trademark Office.

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Is a
Patent
Patent
1

Patent attributes

Patent Applicant
Tesla (company)
Tesla (company)
1
Current Assignee
Tesla (company)
Tesla (company)
1
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
1
Patent Number
114030691
Patent Inventor Names
Kevin Altair Hurd1
Emil Talpes1
Peter Joseph Bannon1
Date of Patent
August 2, 2022
1
Patent Application Number
168877841
Date Filed
May 29, 2020
1
Patent Citations
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US Patent 10833785 Processing communications signals using a machine-learning network
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US Patent 10908606 Autonomous navigation based on road signatures
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US Patent 10909368 Crop type classification in images
1
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US Patent 10909453 Method of controlling for undesired factors in machine learning models
1
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US Patent 10915783 Detecting and locating actors in scenes based on degraded or supersaturated depth data
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US Patent 10917522 Automated call requests with status updates
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US Patent 10921817 Point cloud filtering with semantic segmentation
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US Patent 10922578 Change detection based imagery acquisition tasking system
...
Patent Citations Received
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US Patent 11698773 Accelerated mathematical engine
265
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US Patent 11561791 Vector computational unit receiving data elements in parallel from a last row of a computational array
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US Patent 11679780 Methods and systems for monitoring vehicle motion with driver safety alerts
268
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US Patent 11681649 Computational array microprocessor system using non-consecutive data formatting
269
Patent Primary Examiner
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Aaron W Carter
1
CPC Code
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G06F 7/575
1
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G06F 7/50
1
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G06F 7/52
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G06F 7/5443
1
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G06F 15/80
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G06F 17/16
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G06N 3/0454
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G06N 3/063
1
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Various embodiments of the disclosure relate to an accelerated mathematical engine. In certain embodiments, the accelerated mathematical engine is applied to image processing such that convolution of an image is accelerated by using a two-dimensional matrix processor comprising sub-circuits that include an ALU, output register and shadow register. This architecture supports a clocked, two-dimensional architecture in which image data and weights are multiplied in a synchronized manner to allow a large number of mathematical operations to be performed in parallel.

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