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US Patent 11335693 3-dimensional NOR strings with segmented shared source regions

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Is a
Patent
Patent
0

Patent attributes

Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
0
Patent Number
113356930
Patent Inventor Names
Eli Harari0
Raul Adrian Cernea0
Date of Patent
May 17, 2022
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Patent Application Number
171706640
Date Filed
February 8, 2021
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Patent Citations
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US Patent 10096364 Three-dimensional vertical NOR flash thin-film transistor strings
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US Patent 10121553 Capacitive-coupled non-volatile thin-film transistor NOR strings in three-dimensional arrays
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US Patent 10249370 Three-dimensional vertical NOR flash thing-film transistor strings
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US Patent 10254968 Hybrid memory device for lookup operations
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US Patent 10373956 Gated bipolar junction transistors, memory arrays, and methods of forming gated bipolar junction transistors
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US Patent 10381378 Three-dimensional vertical NOR flash thin-film transistor strings
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US Patent 10395737 Three-dimensional vertical NOR flash thin-film transistor strings
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US Patent 10431596 Staggered word line architecture for reduced disturb in 3-dimensional NOR memory arrays
...
Patent Citations Received
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US Patent 12073082 High capacity memory circuit with low effective latency
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US Patent 11915768 Memory circuit, system and method for rapid retrieval of data sets
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US Patent 12002523 Memory circuit, system and method for rapid retrieval of data sets
0
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US Patent 11751388 3-dimensional nor strings with segmented shared source regions
Patent Primary Examiner
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Tan T. Nguyen
0

A NOR string includes a number of individually addressable thin-film storage transistors sharing a bit line, with the individually addressable thin-film transistors further grouped into a predetermined number of segments. In each segment, the thin-film storage transistors of the segment share a source line segment, which is electrically isolated from other source line segments in the other segments within the NOR string. The NOR string may be formed along an active strip of semiconductor layers provided above and parallel a surface of a semiconductor substrate, with each active strip including first and second semiconductor sublayers of a first conductivity and a third semiconductor sublayer of a second conductivity, wherein the shared bit line and each source line segment are formed in the first and second semiconductor sublayers, respectively.

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