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US Patent 11335391 Memory cell arrangement and method thereof

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
Date Filed
October 30, 2020
Date of Patent
May 17, 2022
Patent Application Number
17085084
Patent Citations Received
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US Patent 11950430 Memory cell, capacitive memory structure, and methods thereof
0
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US Patent 12075625 Memory cell, capacitive memory structure, and methods thereof
0
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US Patent 12096638 One transistor and N memory element based memory bit-cell having stacked and folded planar memory elements with and without offset
0
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US Patent 12094511 Write disturb mitigation for column multiplexed non-linear polar material based multi-capacitor bit-cell
0
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US Patent 12087730 Multi-input threshold gate having stacked and folded planar capacitors with and without offset
0
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
11335391
Patent Primary Examiner
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Khamdan N. Alrobaie
CPC Code
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H01L 27/11507
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G11C 11/2275
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G11C 11/2273
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G11C 11/221

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