Patent attributes
A display device having a gate driver, which may reduce a leakage current of a TFT and power consumption, is disclosed. Each stage of the gate driver comprises an output portion including a pull-up transistor outputting a corresponding clock of a plurality of clocks as a gate signal in response to control of a Q node, and a pull-down transistor outputting a gate-off voltage as an off-voltage of a gate signal in response to control of a QB node; a controller charging and discharging the Q node and charging and discharging the QB node to be in an opposite state of the Q node; and a back bias circuit having a back bias node capacitance-coupled with the Q node and generating a back gate bias voltage to apply the back gate bias voltage to the back bias node for an off-period of the Q node, wherein the back bias circuit may apply the back gate bias voltage to light shielding layers of some transistors, which are turned off for the off-period of the Q node, among transistors constituting the output portion and the controller, through the back bias node, thereby reducing or minimizing a leakage current of the corresponding transistors.
