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US Patent 11296806 Shared communication channel that interleaves 1 PPS signals and messaging

Patent 11296806 was granted and assigned to Skyworks Solutions on April, 2022 by the United States Patent and Trademark Office.

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Contents

Is a
Patent
Patent
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Patent attributes

Patent Applicant
Skyworks Solutions
Skyworks Solutions
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Current Assignee
Skyworks Solutions
Skyworks Solutions
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
112968060
Patent Inventor Names
Robert P. Coulter0
Date of Patent
April 5, 2022
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Patent Application Number
162352320
Date Filed
December 28, 2018
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Patent Citations
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US Patent 10536258 Skew compensation for multi-domain clock generation
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US Patent 10594423 Re-timing a packetized radio flow to clean noise induced by packet delay variation of a packet network
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US Patent 10715307 Embedded time of day receiver for clock transmission
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US Patent 10727845 Use of a virtual clock in a PLL to maintain a closed loop system
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US Patent 10797686 Phase predictor and associated method of use
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US Patent 10917097 Circuits and methods for transferring two differentially encoded client clock domains over a third carrier clock domain between integrated circuits
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US Patent 10511312 Metastable-free output synchronization for multiple-chip systems and the like
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US Patent 10158444 Event-driven precision time transfer
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Patent Citations Received
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US Patent 11977178 Multi-chip synchronization for digital radars
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US Patent 11863299 Shared communication channel that interleaves 1 PPS signals and messaging
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US Patent 11545982 Type-I PLLs for phase-controlled applications
Patent Primary Examiner
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Edan Orgad
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CPC Code
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H04W 84/20
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H04L 12/66
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H04L 49/351
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H04L 12/5601
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H04L 25/4902
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H04L 7/033
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H04L 49/30
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H04L 67/42
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A shared bus time interleaves 1 PPS signal and control and coordination information between a primary timing source and line cards that need to be synchronized using the 1 PPS signals. The shared bus utilizes 1 second frames divided into time slots. The 1 PPS signals are interleaved at predetermined locations in the frame so the delays introduced by interleaving the 1 PPS data in time can be precisely removed. While the bus is not being used for 1 PPS signals, the bus is available to send control and coordination information between the line cards and the primary timing source, avoiding the use of another system and increasing utilization of an available communication path.

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