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US Patent 11296710 Digital subsampling PLL with DTC-based SAR phase estimation

Patent 11296710 was granted and assigned to Qorvo on April, 2022 by the United States Patent and Trademark Office.

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
Current Assignee
Qorvo
Qorvo
Date Filed
August 24, 2020
Date of Patent
April 5, 2022
Patent Applicant
Qorvo
Qorvo
Patent Application Number
17000647
Patent Citations
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US Patent 10895850 Mixed-domain circuit with differential domain-converters
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US Patent 10996634 System and method for fast-converging digital-to-time converter (DTC) gain calibration for DTC-based analog fractional-N phase lock loop (PLL)
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US Patent 10917078 System and method for fast converging reference clock duty cycle correction for digital to time converter (DTC)-based analog fractional-N phase-locked loop (PLL)
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US Patent 10224942 Sub-sampling phase-locked loop
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US Patent 10291214 Feedforward phase noise compensation
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US Patent 10581418 System and method for fast converging reference clock duty cycle correction for digital to time converter (DTC)-based analog fractional-N phase-locked loop (PLL)
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US Patent 10615807 Sub-sampling phase-locked loop
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US Patent 10862496 High-speed successive-approximation-register (SAR) analog-to-digital converter (ADC) control logic circuit
Patent Citations Received
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US Patent 11659302 Differential subrange ADC for image sensor
0
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US Patent 11387833 Differential digital-to-time converter for even-order INL cancellation and supply noise/disturbance rejection
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
11296710
Patent Primary Examiner
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Berhanu Tadese
CPC Code
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H03L 7/091
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H03L 7/0991
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H03L 7/093
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H03L 7/081

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