US Patent 11282414 Reduced overhead gate level logic encryption

There are several approaches to encrypting circuits: combination logic encryption, encrypted gate topologies, transmission gate topologies, and key expansion of gate topologies. One of the approaches provides a circuit having a gate topology comprising a logic gate with integrated key transistors, where the key transistors comprise at least a PMOS stack and an NMOS stack. The PMOS stack comprises a first PMOS switch and a second PMOS switch, where the first and the second PMOS switches have sources to a voltage source and drains that serve as a source to a third PMOS switch. The NMOS stack comprises a first NMOS switch and a second NMOS switch, where the first and the second NMOS switches have sources to ground and drains that serve as a source to a third NMOS switch. Each of the above approaches may encrypt a circuit with certain advantages in delay and power consumption.