US Patent 11257455 Gate drive circuit and display panel

A gate drive circuit and a display panel are provided. The gate drive circuit includes N clock signal lines and a plurality of gate drive units. Each of the gate drive units is connected to at least one of the clock signal lines. Each of the clock signal lines is provided with a capacitance compensation unit, a sum of an area of any one of the clock signal lines and an area of the capacitance compensation unit provided on the same clock signal line is equal to a predetermined area, and N is an integer greater than or equal to 2.