US Patent 11164780 Process integration approach for selective metal via fill

Methods and apparatus for an interconnect formed on a substrate and a method of forming the interconnect thereon. In embodiments, the methods include etching through a hard mask disposed atop a low-k dielectric layer to form a via through the low-k dielectric layer and expose a conductive surface; contacting the conductive surface with dilute hydrofluoric acid to remove contaminants therefrom; removing the hard mask disposed atop the low-k dielectric layer; and applying a remote hydrogen plasma to the conductive surface to form an exposed portion of the conductive surface.