Patent attributes
A memory device may include a memory cell array, a program and verify circuit, a verify table storage, and a program fail detector. The memory cell array may include memory cells. The program and verify circuit may perform a program operation of programming the memory cells to a corresponding target state of a plurality of states, and generate verification data including cell count values that respectively correspond to one or more states among the plurality of states. The verify table storage may store, for each program pulse count, reference data including reference cell count values that respectively correspond to the plurality of states. The program fail detector may detect whether the program operation has failed based on a result of a comparison between the verification data and the reference data corresponding to a current program pulse count, and generate program fail information indicating that the program operation has failed.
