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US Patent 11055062 Switched capacitor vector-matrix multiplier

Patent 11055062 was granted and assigned to Areanna Inc. on July, 2021 by the United States Patent and Trademark Office.

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
Current Assignee
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Areanna Inc.
Date Filed
February 11, 2019
Date of Patent
July 6, 2021
Patent Applicant
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Areanna Inc.
Patent Application Number
16272901
Patent Citations
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US Patent 10594334 Mixed-mode multipliers for artificial intelligence
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US Patent 10417460 Low power analog vector-matrix multiplier
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US Patent 10389375 System and methods for mixed-signal computing
Patent Citations Received
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US Patent 12118331 Bias unit element with binary weighted charge transfer lines
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US Patent 11476866 Successive approximation register using switched unit elements
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US Patent 11567730 Layout structure for shared analog bus in unit element multiplier
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US Patent 11842167 Switched capacitor vector-matrix multiplier
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US Patent 11922240 Unit element for asynchronous analog multiplier accumulator
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US Patent 12026479 Differential unit element for multiply-accumulate operations on a shared charge transfer bus
0
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US Patent 11469770 Architecture for multiplier accumulator using unit elements for multiplication, bias, accumulation, and analog to digital conversion over a shared charge transfer bus
0
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US Patent 11689213 Architecture for analog multiplier-accumulator with binary weighted charge transfer capacitors
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Patent Inventor Names
Behdad Youssefi
0
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
11055062
Patent Primary Examiner
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Tan V. Mai

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