Patent attributes
A method of designing a 3D Integrated Circuit, the method including: performing partitioning to at least a logic strata including logic and a memory strata including memory; then performing a first placement of the logic strata using a 2D placer executed by a computer, where the 2D placer is a Computer Aided Design (CAD) tool for two-dimensional devices; where the 3D Integrated Circuit includes through silicon vias for connection between the logic strata and the memory strata; and performing a second placement of the memory strata based on the first placement, where the logic includes at least one decoder representation for the memory, where the at least one decoder representation has a virtual size with width of contacts for the through silicon vias, and where the performing a first placement includes using the decoder representation instead of an actual memory decoder.
