Patent attributes
Enhanced address space layout randomization is disclosed. For example, a memory includes first and second memory addresses of a plurality of memory addresses, where at least one of the plurality of memory addresses is a decoy address. A memory manager executes on a processors to generate a page table associated with the memory, which includes a plurality of page table entries. Each page table entry in the plurality of page table entries is flagged as in a valid state. The page table is instantiated with first and second page table entries of the plurality of page table entries associated with the first and second memory addresses respectively. A plurality of unused page table entries of the plurality of page table entries, including a decoy page table entry, is associated with a decoy address.
