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US Patent 11023633 High-level synthesis method, high-level synthesis apparatus, and high-level synthesis system

Patent 11023633 was granted and assigned to Renesas Electronics on June, 2021 by the United States Patent and Trademark Office.

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Patent
Patent
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Patent attributes

Patent Applicant
Renesas Electronics
Renesas Electronics
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Current Assignee
Renesas Electronics
Renesas Electronics
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
110236330
Patent Inventor Names
Shintaro Imamura0
Date of Patent
June 1, 2021
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Patent Application Number
168202040
Date Filed
March 16, 2020
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Patent Citations
‌
US Patent 10685159 Analog functional safety with anomaly detection
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US Patent 10761951 FPGA based functional safety control logic (FFSCL)
Patent Primary Examiner
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Sun J Lin
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Patent abstract

Disclosed herein is a method of generating an RTL description that implements any functional safety system. A high-level synthesis method for generating an RTL description in which a functional safety system is inserted by using an operation description defining a functional logic, a high-level synthesis script defining a high-level synthesis constraint, and a functional safety system implementation specification specifying a functional safety system to be inserted in a high-level synthesis process. The high-level synthesis method includes a control data flow graph generation step in which a high-level synthesis unit generates a control data flow graph using the operation description, and a first function safety system insertion processing step in which the high-level synthesis unit inserts the function safety system into the control data flow graph according to the function safety system implementation specification after the control data flow graph generation step.

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