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US Patent 11018695 Fast-converging bit-flipping decoder for low-density parity-check codes
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Patent
Date Filed
November 11, 2019
Date of Patent
May 25, 2021
Patent Application Number
16680330
Patent Citations
US Patent 10200064 Systems and method for bit-flipping decoders with partial-column processing, ordering and scheduling
Patent Citations Received
US Patent 12127016 Providing configuration updates to wireless telecommunication networks
0
US Patent 11765604 Providing configuration updates to wireless telecommunication networks
US Patent 11777522 Bit flipping decoder with dynamic bit flipping criteria
US Patent 11398835 Managing defective bitline locations in a bit flipping decoder
0
US Patent 11923868 Stall mitigation in iterative decoders
0
US Patent 11923867 Iterative decoder with a dynamic maximum stop condition
0
US Patent 11469775 Method for decoding inertia-effect bit-flip LDPC codes
Patent Inventor Names
Fan Zhang
0
Jiangnan Xia
0
Chenrong Xiong
0
Haobo Wang
0
Hongwei Duan
0
Patent Jurisdiction
United States Patent and Trademark Office
Patent Number
11018695
Patent Primary Examiner
Christine T. Tu
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