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US Patent 10997345 Method of etch model calibration using optical scatterometry

Patent 10997345 was granted and assigned to Lam Research on May, 2021 by the United States Patent and Trademark Office.

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Is a
Patent
Patent
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Patent attributes

Patent Applicant
Lam Research
Lam Research
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Current Assignee
Lam Research
Lam Research
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
109973450
Patent Inventor Names
Ye Feng0
Mehmet Derya Tetiker0
Saravanapriyan Sriraman0
Yan Zhang0
Andrew D. Bailey, III0
Julien Mailfert0
Marcus Musselman0
Date of Patent
May 4, 2021
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Patent Application Number
167417350
Date Filed
January 13, 2020
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Patent Citations
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US Patent 10534257 Layout pattern proximity correction through edge placement error prediction
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US Patent 10585347 Photoresist design layout pattern proximity correction through fast edge placement error prediction via a physics-based etch profile modeling framework
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US Patent 10572697 Method of etch model calibration using optical scatterometry
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US Patent 10032681 Etch metric sensitivity for endpoint detection
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US Patent 10197908 Photoresist design layout pattern proximity correction through fast edge placement error prediction via a physics-based etch profile modeling framework
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US Patent 10254641 Layout pattern proximity correction through fast edge placement error prediction
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US Patent 10303830 Methods and apparatuses for etch profile optimization by reflectance spectra matching and surface kinetic model optimization
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US Patent 10386828 Methods and apparatuses for etch profile matching by surface kinetic model optimization
Patent Citations Received
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US Patent 11921433 Optical metrology in machine learning to characterize features
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US Patent 11624981 Resist and etch modeling
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US Patent 11704463 Method of etch model calibration using optical scatterometry
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Patent Primary Examiner
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Bryce M Aisaka
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Patent abstract

Computer-implemented methods of optimizing a process simulation model that predicts a result of a semiconductor device fabrication operation to process parameter values characterizing the semiconductor device fabrication operation are disclosed. The methods involve generating cost values using a computationally predicted result of the semiconductor device fabrication operation and a metrology result produced, at least in part, by performing the semiconductor device fabrication operation in a reaction chamber operating under a set of fixed process parameter values. The determination of the parameters of the process simulation model may employ pre-process profiles, via optimization of the resultant post-process profiles of the parameters against profile metrology results. Cost values for, e.g., optical scatterometry, scanning electron microscopy and transmission electron microscopy may be used to guide optimization.

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