Patent attributes
A device and method for controllably delaying an electrical signal includes a first signal transfer path between a signal input and a signal output. The first signal transfer path includes a first signal transfer stage with a first differential pair and a common, adjustable first quiescent current source, and a second signal transfer path between the signal input and the signal output. The second signal transfer path includes a second signal transfer stage with a second differential pair and a common, adjustable second quiescent current source. An internal delay stage is arranged between the signal input and the second signal transfer stage and has a third differential pair and a common, adjustable third quiescent current source, and signal combination stage for additively superimposing the electrical signal transferred via the first signal transfer path on to the electrical signal transferred via the second signal transfer path.
