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US Patent 10915297 Hardware accelerator for systolic matrix multiplication
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Is a
Patent
Date Filed
November 12, 2018
Date of Patent
February 9, 2021
Patent Applicant
Habana Labs Ltd
Patent Application Number
16186620
Patent Citations
US Patent 10685082 Sparse matrix multiplication using a single field programmable gate array module
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US Patent 10387122 Residue number matrix multiplier
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Patent Citations Received
US Patent 11467806 Systolic array including fused multiply accumulate with efficient prenormalization and extended dynamic range
US Patent 11520371 Compute-adaptive clock management for machine learning accelerators
US Patent 11842169 Systolic multiply delayed accumulate processor architecture
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US Patent 11880682 Systolic array with efficient input reduction and extended array performance
0
US Patent 12007937 Multi-mode architecture for unifying matrix multiplication, 1×1 convolution and 3×3 convolution
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US Patent 12008069 Multi-mode architecture for unifying matrix multiplication, 1×1 convolution and 3×3 convolution
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US Patent 12067375 Systolic array including fused multiply accumulate with efficient prenormalization and extended dynamic range
0
US Patent 11762803 Multiple accumulate busses in a systolic array
US Patent 11423292 Convolutional neural-network calculating apparatus and operation methods thereof
Patent Inventor Names
Tomer Rothschild
0
Ran Halutz
0
Ron Shalev
0
Patent Jurisdiction
United States Patent and Trademark Office
Patent Number
10915297
Patent Primary Examiner
Andrew Caldwell
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