US Patent 10896956 Field effect transistor with reduced contact resistance

FET transistor (100) comprising:a semiconductor portion (104) of which a first part (106) forms a channel;a gate (108) at least partly surrounding the first part;internal dielectric spacers (112) arranged around doped second parts (114) of the semiconductor portion between which the first part is arranged and which form extension regions;electrically conductive portions (120) in contact with doped surfaces of extremities (118) of the semiconductor portion and with doped surfaces of third parts (116) of the semiconductor portion, forming part of the source and drain regions, at least partly surrounding the third parts, with each of the second parts being arranged between the first part and one of the third parts.