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US Patent 10884956 I/O bus shared memory system
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Patent
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Date Filed
July 20, 2016
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Date of Patent
January 5, 2021
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Patent Application Number
15215439
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Patent Citations
US Patent 10657092 Innovative high speed serial controller testing
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US Patent 10664433 Innovative high speed serial controller testing
US Patent 10056155 Systems, methods, and apparatuses for implementing testing of a far memory subsystem within two-level memory (2LM) stacked die subsystems
US Patent 10249597 Systems, methods, and apparatuses for implementing die recovery in two-level memory (2LM) stacked die subsystems
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US Patent 10484361 Systems, methods, and apparatuses for implementing a virtual device observation and debug network for high speed serial IOS
Patent Citations Received
US Patent 11273906 Redundant fly-by-wire systems with fault resiliency
Patent Inventor Names
Kuen-Long Chang
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Chin-Hung Chang
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Ken-Hui Chen
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
10884956
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Patent Primary Examiner
Henry Tsai
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