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US Patent 10853541 Data processing engine (DPE) array global mapping

Patent 10853541 was granted and assigned to Xilinx on December, 2020 by the United States Patent and Trademark Office.

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Patent Citations Received
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US Patent 12001370 Multi-node memory address space for PCIe devices
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Patent Citations Received
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US Patent 11687327 Control and reconfiguration of data flow graphs on heterogeneous computing platform
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edited on 24 May, 2023
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Official Website
https://pdfpiw.uspto.gov/.piw?Docid=1085354100
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Infobox
Is a
Patent
Patent
0
Patent Applicant
Xilinx
Xilinx
0
Current Assignee
Xilinx
Xilinx
0
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
0
Patent Number
108535410
Date of Patent
December 1, 2020
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Patent Application Number
163996610
Date Filed
April 30, 2019
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Official Website
https://pdfpiw.uspto.gov/.piw?Docid=108535410
Patent Citations
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US Patent 10068045 Programmable logic device design implementations with multiplexer transformations
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US Patent 10324740 Enhanced control system for flexible programmable logic and synchronization
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US Patent 10516396 Overlay architecture for programming FPGAs
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Patent Citations Received
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US Patent 11301295 Implementing an application specified as a data flow graph in an array of data processing engines
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US Patent 11474826 Boot image file having a global partition for data processing engines of a programmable device
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Patent Primary Examiner
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Helen Rossoshek
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Edits on 26 Apr, 2023
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Website URL
https://pdfpiw.uspto.gov/.piw?Docid=10853541
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 US Patent 10853541 Data processing engine (DPE) array global mapping

Infobox
Is a
Patent
Patent
Patent applicant
Xilinx
Xilinx
Current assignee
Xilinx
Xilinx
Patent jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent number
10853541
Date of patent
December 1, 2020
Patent application number
16399661
Date Filed
April 30, 2019
Patent citations
‌
US Patent 10068045 Programmable logic device design implementations with multiplexer transformations
‌
US Patent 10324740 Enhanced control system for flexible programmable logic and synchronization
‌
US Patent 10516396 Overlay architecture for programming FPGAs
Patent primary examiner
‌
Helen Rossoshek

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