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US Patent 10831938 Parallel power down processing of integrated circuit design
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Patent
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Date Filed
August 14, 2019
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Date of Patent
November 10, 2020
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Patent Application Number
16540094
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Patent Citations
US Patent 10031986 System and method for creating a spice deck for path-based analysis of an electronic circuit design using a stage-based technique
US Patent 10333535 Techniques for signal skew compensation
Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
10831938
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Patent Primary Examiner
Helen Rossoshek
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