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US Patent 10790280 Multi-gate device and method of fabrication thereof
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Patent
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Date Filed
February 2, 2018
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Date of Patent
September 29, 2020
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Patent Application Number
15887347
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Patent Citations
US Patent 10103065 Gate metal patterning for tight pitch applications
US Patent 10128122 Stacked nanowires
US Patent 10141403 Integrating thin and thick gate dielectric nanosheet transistors on same chip
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US Patent 10157799 Multi-gate device and method of fabrication thereof
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US Patent 10181510 Semiconductor device and method for fabricating the same
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US Patent 10269790 Forming horizontal bipolar junction transistor compatible with nanosheets
US Patent 10243040 Semiconductor device
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US Patent 10355137 FINFETs with wrap-around silicide and method forming the same
US Patent 10002939 Nanosheet transistors having thin and thick gate dielectric material
US Patent 10008575 Semiconductor device and method of fabricating the same
Patent Citations Received
US Patent 11600625 Semiconductor device having an offset source/drain feature and method of fabricating thereof
US Patent 11476328 Stacked nanowire or nanosheet gate-all-around device and method for manufacturing the same
Patent Jurisdiction
United States Patent and Trademark Office
0
Patent Number
10790280
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Patent Primary Examiner
Sophia T Nguyen
0
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