US Patent 10740248 Methods and systems for predicting virtual address

Patent

US Patent 12118360 Branch target buffer miss handling

US Patent 12014180 Dynamically foldable and unfoldable instruction fetch pipeline

US Patent 12020032 Prediction unit that provides a fetch block descriptor each clock cycle

US Patent 12106111 Prediction unit with first predictor that provides a hashed fetch address of a current fetch block to its own input and to a second predictor that uses it to predict the fetch address of a next fetch block

US Patent 11836498 Single cycle predictor

US Patent 11880685 Folded instruction fetch pipeline

US Patent 11977893 Folded instruction fetch pipeline

US Patent 12008375 Branch target buffer that stores predicted set index and predicted way number of instruction cache

US Patent 12014178 Folded instruction fetch pipeline

United States Patent and Trademark Office

Ryan Bertram