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US Patent 10593690 Hybrid bonding contact structure of three-dimensional memory device

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Patent
Patent
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Patent attributes

Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
0
Patent Number
105936900
Patent Inventor Names
Feng Pan0
Guanping Wu0
Jun Chen0
Weihua Cheng0
Wenguang Shi0
Zhenyu Lu0
Simon Shi-Ning Yang0
Steve Weiyi Yang0
Date of Patent
March 17, 2020
0
Patent Application Number
160468520
Date Filed
July 26, 2018
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Patent Citations Received
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US Patent 12137568 Hybrid bonding contact structure of three-dimensional memory device
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US Patent 11462558 Staircase structure with multiple divisions for three-dimensional memory
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US Patent 11482536 Electronic devices comprising memory pillars and dummy pillars including an oxide material, and related systems and methods
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US Patent 11527547 Hybrid bonding contact structure of three-dimensional memory device
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US Patent 10923491 Hybrid bonding contact structure of three-dimensional memory device
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US Patent 11031333 Three-dimensional memory devices having a plurality of NAND strings
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US Patent 11056387 Method for forming three-dimensional integrated wiring structure and semiconductor structure thereof
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US Patent 11699657 Three-dimensional memory devices having a plurality of NAND strings located between a substrate and a single crystalline silicon layer
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Patent Primary Examiner
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Reema Patel
0
Patent abstract

Embodiments of through array contact structures of a 3D memory device and fabricating method thereof are disclosed. The memory device includes an alternating layer stack disposed on a first substrate. The alternating layer stack includes a first region including an alternating dielectric stack, and a second region including an alternating conductor/dielectric stack. The memory device further includes a barrier structure extending vertically through the alternating layer stack to laterally separate the first region from the second region, multiple through array contacts in the first region, each through array contact extending vertically through the alternating dielectric stack, an array interconnection layer in contact with the through array contacts, a peripheral circuit formed on a second substrate. and a peripheral interconnection layer on the peripheral circuit. The array interconnection layer is bonded on the peripheral interconnection layer, such that the peripheral circuit is electrically connected with at least one through array contact.

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