Patent attributes
A selected ferroelectric memory cell of a ferroelectric memory is electrically connected to a first bit line, a second bit line, a first word line, a second word line and a plate line. The selected ferroelectric memory cell includes a first field effect transistor (“FET”), a second FET and a ferroelectric capacitor. A control terminal and a first access terminal of the first FET are electrically connected to the first word line and the first bit line, respectively. A control terminal and a first access terminal of the second FET are electrically connected to the second word line and the second bit line, respectively. A second access terminal of the first FET is electrically connected to a first capacitor electrode of the ferroelectric capacitor and a second access terminal of the second FET. A second capacitor electrode of the ferroelectric capacitor is electrically connected to the plate line.
