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US Patent 10528864 Sparse convolutional neural network accelerator

Patent 10528864 was granted and assigned to NVIDIA on January, 2020 by the United States Patent and Trademark Office.

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Is a
Patent
Patent
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Patent attributes

Patent Applicant
NVIDIA
NVIDIA
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Current Assignee
NVIDIA
NVIDIA
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
105288640
Patent Inventor Names
Angshuman Parashar0
Larry Robert Dennison0
Stephen William Keckler0
William J. Dally0
Joel Springer Emer0
Date of Patent
January 7, 2020
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Patent Application Number
154587990
Date Filed
March 14, 2017
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Patent Citations Received
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US Patent 11488005 Smart autonomous machines utilizing cloud, error corrections, and predictions
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US Patent 11488008 Hardware implemented point to point communication primitives for machine learning
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US Patent 11494967 Scatter gather engine
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US Patent 11494187 Message based general register file assembly
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US Patent 11494232 Memory-based software barriers
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US Patent 11501152 Efficient learning and using of topologies of neural networks in machine learning
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US Patent 11501139 Scaling half-precision floating point tensors for training deep neural networks
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US Patent 11508338 Register spill/fill using shared local memory space
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Patent Primary Examiner
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Kamran Afshar
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Patent abstract

A method, computer program product, and system perform computations using a sparse convolutional neural network accelerator. A first vector comprising only non-zero weight values and first associated positions of the non-zero weight values within a 3D space is received. A second vector comprising only non-zero input activation values and second associated positions of the non-zero input activation values within a 2D space is received. The non-zero weight values are multiplied with the non-zero input activation values, within a multiplier array, to produce a third vector of products. The first associated positions are combined with the second associated positions to produce a fourth vector of positions, where each position in the fourth vector is associated with a respective product in the third vector. The products in the third vector are transmitted to adders in an accumulator array, based on the position associated with each one of the products.

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