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US Patent 10417555 Data-optimized neural network traversal

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Patent
Patent
0

Patent attributes

Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
0
Patent Number
104175550
Patent Inventor Names
John W. Brothers0
Joohoon Lee0
Date of Patent
September 17, 2019
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Patent Application Number
151486270
Date Filed
May 6, 2016
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Patent Citations Received
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US Patent 11467968 Memory-adaptive processing method for convolutional neural network
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US Patent 11550543 Semiconductor memory device employing processing in memory (PIM) and method of operating the semiconductor memory device
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US Patent 11556798 Optimizing machine learning model performance
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US Patent 10963390 Memory-adaptive processing method for convolutional neural network and system thereof
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US Patent 11074317 System and method for cached convolution calculation
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US Patent 11822898 Semiconductor memory device employing processing in memory (PIM) and method of operating the semiconductor memory device
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Patent Primary Examiner
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Vincent Gonzales
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Patent abstract

Executing a neural network includes generating an output tile of a first layer of the neural network by processing an input tile to the first layer and storing the output tile of the first layer in an internal memory of a processor. An output tile of a second layer of the neural network can be generated using the processor by processing the output tile of the first layer stored in the internal memory.

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