Patent attributes
An interface circuit for supplying a plurality of data signals to a data reception circuit includes a timing signal generating circuit configured to generate a timing signal. The timing signal indicates a timing to switch operation of the interface circuit between a data input mode and a non-input mode. The interface circuit further includes a data control circuit configured to control a supply of the data signals to the data reception circuit in the data input mode, a plurality of abnormality detection circuits each configured to detect an abnormality that has occurred in the data reception circuit, and a select circuit configured to select one abnormality detection circuit based on each of the data signals supplied in the non-input mode of the interface circuit, and output, as an abnormality detection signal, a detection result of the selected one of the abnormality detection circuits.
