US Patent 10361702 FPGA math block with dedicated connections

An architecture in a user-programmable integrated circuit includes a hard logic block having inputs and outputs, a first group of user-configurable general-purpose routing resources coupled to first selected ones of the inputs of the hard logic block, a soft logic block having inputs and outputs, first selected ones of the inputs of the soft logic block coupled to the first group of user-configurable general-purpose routing resources, first selected ones of the outputs of the soft logic block having dedicated connections to second selected ones of the inputs to the hard logic block, and a second group of user-configurable general-purpose routing resources coupled to second selected ones of the outputs of the soft logic block and to first selected ones of the outputs of the hard logic block.