Patent attributes
There is disclosed a self-timed processor. The self-timed processor includes trigger logic having a trigger input to receive an event trigger signal, a data input set to data value 1, a trigger output to send a trigger output signal when the event trigger signal is received, and a reset input to reset the trigger output signal. The processor also has a delay insensitive asynchronous logic (DIAL) block with multi-rail DIAL inputs to receive a multi-rail DIAL input having a) the trigger output signal, and b) data value 0; and data phase completion logic to output a completion signal indicating an end of a data propagate phase of the DIAL block to reset the trigger output signal when multi-rail data DIAL data process values of the DIAL block reach a DIAL valid state.
