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US Patent 10320509 Fail safe clock buffer and clock generator

OverviewStructured DataIssuesContributors
Is a
Patent
Patent
Date Filed
December 28, 2015
Date of Patent
June 11, 2019
Patent Application Number
14980036
Patent Citations Received
‌
US Patent 11342926 Synchronization of clock signals generated using output dividers
‌
US Patent 10908635 Detection and management of frequency errors in a reference input clock signal
‌
US Patent 10951216 Synchronization of clock signals generated using output dividers
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
10320509
Patent Primary Examiner
‌
Phuongchau Ba Nguyen

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