US Patent 10320390 Field programmable gate array including coupled lookup tables

A reconfigurable field programmable gate array (FPGA) includes: a first logic block having a first lookup table; and a second logic block having a second lookup table, wherein the first logic block is coupled to the second logic block, in which the first logic block is configured to pass, upon a clock cycle of the FPGA, data about a lookup table configuration stored in the first lookup table to the second logic block.