US Patent 10319449 Memory device and operation method thereof

A memory device is provided. The memory device includes: a memory array having a plurality of cells; a regulator, coupled to the memory, the regulator being configured to provide a bit line voltage to a selected cell of the memory array and to provide a bias voltage; and a controllable current source, coupled to the memory array, the controllable current source being configured to conduct a controllable current in the controllable current source until a cell current of the selected cell reaches a threshold.