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US Patent 10313105 Fractional-N PLL based clock recovery for SerDes
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Patent
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Date Filed
September 12, 2017
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Date of Patent
June 4, 2019
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Patent Application Number
15702715
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Patent Citations Received
US Patent 10778236 PLL with wide frequency coverage
US Patent 10892763 Second-order clock recovery using three feedback paths
US Patent 10818608 Cage-shielded interposer inductances
US Patent 11038602 On-chip jitter evaluation for SerDes
US Patent 10992501 Eye monitor for parallelized digital equalizers
US Patent 10727786 Multiport inductors for enhanced signal distribution
Patent Inventor Names
Xiang Gao
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Haoli Qian
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
10313105
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Patent Primary Examiner
Sung S Ahn
0
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