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US Patent 10296556 System and method for efficient sparse matrix processing

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Patent abstractTimelineTable: Further ResourcesReferences
Is a
Patent
Patent
1

Patent attributes

Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
1
Patent Number
102965561
Patent Inventor Names
Rong Zhou1
Date of Patent
May 21, 2019
1
Patent Application Number
156985471
Date Filed
September 7, 2017
1
Patent Citations
‌
US Patent 10067910 System and method for GPU maximum register count optimization applied to general matrix-matrix multiplication
Patent Citations Received
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US Patent 11934863 Architecture to support color scheme-based synchronization for machine learning
4
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US Patent 11934965 Architecture to support tanh and sigmoid operations for inference acceleration in machine learning
5
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US Patent 11966857 Architecture to support tanh and sigmoid operations for inference acceleration in machine learning
6
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US Patent 11995463 Architecture to support color scheme-based synchronization for machine learning
7
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US Patent 11995448 Method and apparatus for performing machine learning operations in parallel on machine learning hardware
8
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US Patent 12112175 Method and apparatus for performing machine learning operations in parallel on machine learning hardware
9
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US Patent 12112174 Streaming engine for machine learning architecture
10
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US Patent 11687837 Architecture to support synchronization between core and inference engine for machine learning
11
...
Patent Primary Examiner
‌
David H. Malzahn
1
Patent abstract

A system and method for efficient sparse matrix processing are provided in one embodiment. A compressed representation of a sparse matrix, the sparse matrix including one or more non-zero entries in one or more of a plurality of portions of the matrix, is obtained by at least one server including one or more streaming multiprocessors, each of the streaming multiprocessors including one or more graphics processing unit (GPU) processor cores. Each of the portions are assigned into one of a plurality of partitions based on a number of the non-zero entries in that portion. For each of the partitions, a predefined number of the GPU processor cores are assigned for processing each of the portions assigned to that partition based on the numbers of the non-zero entries in the portions assigned to that partition. For each of the partitions, each of the portions associated with that partition are processed.

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