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US Patent 10211219 Nonvolatile semiconductor memory device and manufacturing method thereof

Patent 10211219 was granted and assigned to Toshiba Memory Corporation on February, 2019 by the United States Patent and Trademark Office.

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Patent
Patent
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Patent attributes

Current Assignee
Toshiba Memory Corporation
Toshiba Memory Corporation
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
102112190
Patent Inventor Names
Akihiro Nitayama0
Hideaki Aochi0
Hiroyasu Tanaka0
Masaru Kidoh0
Masaru Kito0
Mitsuru Sato0
Ryota Katsumata0
Yasuyuki Matsuoka0
...
Date of Patent
February 19, 2019
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Patent Application Number
156666530
Date Filed
August 2, 2017
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Patent Citations Received
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US Patent 11462474 Three-dimensional memory devices having a plurality of NAND strings
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US Patent 11574682 Semiconductor memory device
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US Patent 11031333 Three-dimensional memory devices having a plurality of NAND strings
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US Patent 11699657 Three-dimensional memory devices having a plurality of NAND strings located between a substrate and a single crystalline silicon layer
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US Patent 11862247 Semiconductor memory device
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US Patent 11985827 Semiconductor device, driving method of semiconductor device, and electronic device
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US Patent 12096630 Staircase structures for electrically connecting multiple horizontal conductive layers of a 3-dimensional memory device
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Patent Primary Examiner
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Michael Lebentritt
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Patent abstract

A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

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