US Patent 10210915 Memory device and semiconductor device including the same

A memory device with reduced latency is provided. The memory device includes a burst read mode with a burst length of M0 (M0 is an integer greater than or equal to 2), a global sense amplifier array, M0 local memory cell arrays <1> to <M0>, and M0 local sense amplifier arrays <1> to <M0>. A memory cell includes a transistor and a capacitor. A local memory cell array <J> (J is an integer from 1 to M0) is stacked over a local sense amplifier array <J>. The local memory cell array <J> comprises M0 blocks <J_1> to <J_M0> differentiated by row, The local sense amplifier array <J> in an idle state retains the data of the block <J_J>. The block <J_J> is specified when the local memory cell array <J> is the first local memory cell array to be accessed in a burst read mode.