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US Patent 10180875 Pool-level solid state drive error correction

Patent 10180875 was granted and assigned to Toshiba Memory Corporation on January, 2019 by the United States Patent and Trademark Office.

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Contents

Is a
Patent
Patent

Patent attributes

Patent Applicant
Toshiba Memory Corporation
Toshiba Memory Corporation
Current Assignee
Toshiba Memory Corporation
Toshiba Memory Corporation
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
10180875
Date of Patent
January 15, 2019
Patent Application Number
15205248
Date Filed
July 8, 2016
Patent Citations Received
‌
US Patent 12137140 Scale out storage platform having active failover
0
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US Patent 11494498 Storage data decryption
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US Patent 11500552 Configurable hyperconverged multi-tenant storage system
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US Patent 11507597 Data replication to meet a recovery point objective
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US Patent 12105620 Storage system buffering
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US Patent 12135878 Programming frequently read data to low latency portions of a solid-state storage array
0
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US Patent 11489668 Secret regeneration in a storage system
‌
US Patent 11240307 Multiple communication paths in a storage system
...
Patent Primary Examiner
‌
Steve N Nguyen
Patent abstract

A method for performing error correction for a plurality of storage drives and a storage appliance comprising a plurality of storage devices is disclosed. In one embodiment, the method includes generating a first set of parity bits from a first set of data of at least one of the plurality of storage devices, the first set of parity bits capable of correcting a first number of error bits of the first set of data. The method further includes generating a second set of parity bits from a concatenated set of the first data and a second set of data from at least another of the plurality of storage devices, the second set of parity bits capable of correcting a second number of error bits of the first set of data, the second number being greater than the first number. The method further includes reading the first set of data and (i) correcting error bits within the first set of data with the first set of parity bits where a number of error bits is less than the first number of error bits; and (ii) correcting error bits within the first set of data with the second set of parity bits where the number of error bits is greater than the first number.

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