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US Patent 10090409 Method for fabricating LDMOS with self-aligned body

Patent 10090409 was granted and assigned to Monolithic Power Systems, Inc. on October, 2018 by the United States Patent and Trademark Office.

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Contents

Is a
Patent
Patent

Patent attributes

Patent Applicant
Monolithic Power Systems, Inc.
Monolithic Power Systems, Inc.
Current Assignee
Monolithic Power Systems, Inc.
Monolithic Power Systems, Inc.
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
10090409
Patent Inventor Names
Zeqiang Yao0
Jeesung Jung0
Ji-Hyoung Yoo0
Joel M. McGregor0
Deming Xiao0
Date of Patent
October 2, 2018
Patent Application Number
15279190
Date Filed
September 28, 2016
Patent Citations Received
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US Patent 12113106 LDMOS with self-aligned body and hybrid source
0
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US Patent 10234629 Method for reducing threading dislocation of semiconductor device
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US Patent 11522053 LDMOS with self-aligned body and hybrid source
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US Patent 10727063 Methods of fabricating high voltage semiconductor devices
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US Patent 11646371 MOSFET transistors with hybrid contact
0
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US Patent 11658481 Source and drain enabled conduction triggers and immunity tolerance for integrated circuits
0
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US Patent 11699752 Laterally diffused MOSFET and method of fabricating the same
0
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US Patent 11322611 Methods for LDMOS and other MOS transistors with hybrid contact
...
Patent Primary Examiner
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Charles Garber
Patent abstract

A method for fabricating a LDMOS device, including: forming a semiconductor substrate; forming a dielectric layer atop the semiconductor substrate and an electric conducting layer on the dielectric layer; forming a first photoresist layer on the electric conducting layer; patterning the first photoresist layer through a first mask to form a first opening; etching the electric conducting layer through the first opening; implanting dopants of a first doping type into the semiconductor substrate through the first opening to form a first body region adjacent to the surface of the semiconductor substrate, and a second body region located beneath the first body region; removing the first photoresist layer; etching the electric conducting layer using a second photoresist layer and a second mask.

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