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US Patent 10069660 Low power SerDes architecture and protocol

OverviewStructured DataIssuesContributors
Is a
Patent
Patent
0
Date Filed
April 13, 2017
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Date of Patent
September 4, 2018
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Patent Application Number
15487045
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Patent Citations Received
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US Patent 12113651 Transmitter equalization optimization for ethernet chip-to-module (C2M) compliance
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US Patent 10944620 Multiplexers with protection switching
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US Patent 11606167 Ethernet data transmission method and communications device
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US Patent 11265096 High accuracy time stamping for multi-lane ports
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US Patent 11711159 High accuracy time stamping for multi-lane ports
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US Patent 11805042 Technologies for timestamping with error correction
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US Patent 11424968 Retimer training during link speed negotiation and link training
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US Patent 11546241 Technologies for timestamping with error correction
Patent Inventor Names
Haoli Qian
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Junqing Sun
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Lawrence Chi Fung Cheng
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
10069660
0
Patent Primary Examiner
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Helene Tayong
0

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