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US Patent 10068903 Methods and apparatus for artificial exciton in CMOS processes

Patent 10068903 was granted and assigned to Texas Instruments on September, 2018 by the United States Patent and Trademark Office.

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Patent abstractTimelineTable: Further ResourcesReferences
Is a
Patent
Patent
1

Patent attributes

Patent Applicant
Texas Instruments
Texas Instruments
1
Current Assignee
Texas Instruments
Texas Instruments
1
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
1
Patent Number
100689031
Patent Inventor Names
Greg Charles Baldwin1
Henry Litzmann Edwards1
Date of Patent
September 4, 2018
1
Patent Application Number
147138021
Date Filed
May 15, 2015
1
Patent Citations Received
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US Patent 11450760 Quantum structures using aperture channel tunneling through depletion region
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US Patent 11300816 Quantum structure incorporating theta angle control
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US Patent 11327345 Quantum structure incorporating phi angle control
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US Patent 11327344 FinFET quantum structures utilizing quantum particle tunneling through oxide
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US Patent 11366345 Semiconductor controlled quantum Pauli interaction gate
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US Patent 11423322 Integrated quantum computer incorporating quantum core and associated classical control circuitry
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US Patent 11533046 System and method of generating quantum unitary noise using silicon based quantum dot arrays
11
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US Patent 10793431 Semiconductor controlled quantum annealing interaction gate
...
Patent Primary Examiner
‌
Lex Malsawma
1
Patent abstract

Methods and apparatus for artificial exciton devices. An artificial exciton device includes a semiconductor substrate; at least one well region doped to a first conductivity type in a portion of the semiconductor substrate; a channel region in a central portion of the well region; a cathode region in the well region doped to a second conductivity type; an anode region in the well region doped to the first conductivity type; a first lightly doped drain region disposed between the cathode region and the channel region doped to the first conductivity type; a second lightly doped drain region disposed between the anode region and the channel region doped to the second conductivity type; and a gate structure overlying the channel region, the gate structure comprising a gate dielectric layer lying over the channel region and a gate conductor material overlying the gate dielectric. Methods are disclosed.

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