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US Patent 10038011 Semiconductor device
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Patent
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Date Filed
August 8, 2017
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Date of Patent
July 31, 2018
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Patent Application Number
15671216
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Patent Citations Received
US Patent 11923372 Semiconductor device
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US Patent 10748987 Methods of forming an array of capacitors, methods of forming an array of memory cells individually comprising a capacitor and a transistor, arrays of capacitors, and arrays of memory cells individually comprising a capacitor and a transistor
US Patent 10903122 Methods of forming an array comprising pairs of vertically opposed capacitors and arrays comprising pairs of vertically opposed capacitors
US Patent 11004869 Semiconductor device
US Patent 11296231 Semiconductor device and method for manufacturing semiconductor device
US Patent 11355179 Semiconductor device and method for driving semiconductor device
US Patent 10304961 Semiconductor device
US Patent 10529720 Memory cell, an array of memory cells individually comprising a capacitor and a transistor with the array comprising rows of access lines and columns of digit lines, a 2T-1C memory cell, and methods of forming an array of capacitors and access transistors there-above
US Patent 10622366 Methods of forming an array comprising pairs of vertically opposed capacitors and arrays comprising pairs of vertically opposed capacitors
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Patent Inventor Names
Kensuke Yoshizumi
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Shunpei Yamazaki
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
10038011
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Patent Primary Examiner
Ratisha Mehta
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