Patent attributes
A semiconductor memory device includes a first memory cell which is capable of being set to any one of at least four threshold voltages, a first bit line, a word line, and a first sense amplifier which is connected to the first bit line. The first sense amplifier applies a charging voltage to the first bit line in a first verification operation in which a first voltage is applied to the word line, does not apply the charging voltage to the first bit line in a second verification operation in which a second voltage higher than the first voltage is applied to the word line, and applies the charging voltage to the first bit line BL in a third verification operation in which a third voltage higher than the second voltage is applied to the word line.
