SBIR/STTR Award attributes
A critical component for enabling anti-jam techniques for implementation in GPS receivers is a high performance Analog to Digital Converter (ADC). The ADCs must have high conversion frequencies to support the modernized GPS receiver architectures and bandwidths while having a very high resolution to provide the dynamic range required to counter potential jamming and interference threats. The goal of this program is to develop advanced ADCs that operate at 100 to 350 MSPS conversion rates with 16 effective number of bits (ENOB) resolution for modernized and advanced GPS receiver applications. A new Pipelined Error Cancellation (PEC) ADC architecture has been formulated which eliminates the requirement for an accurate analog delay circuit to propagate the analog input via an analog delay line. The PEC incorporates pipelined LMS error cancellation together with residue error correction to achieve 16 Effective Number of Bits (ENOB) at conversion frequencies greater than 100MHz. The Phase III effort will focus on design, fabrication, and testing of a prototype PEC ADC ASIC.
